Resource sharing to reduce implementation costs in a multicore processor
US8516196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.