Patent · US Active

Clocking scheme for bridge system

US8516290B1 · kind B1 · utility

9Cited by
2References
13Claims
0Family size

Assignee

Inventor

Key dates

Filing dateFeb 2, 2010
Grant dateAug 20, 2013
Priority date
Expiry dateNov 23, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F13/405
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.