Automatic test pattern generation system for programmable logic devices
US8516322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2009 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Jul 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3183
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.