Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
US8516416B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Sep 5, 2012 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Sep 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.