Method and system for mapping memory when selecting an electronic product
US8516433B1 · kind B1 · utility
2Cited by
20References
30Claims
0Family size
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Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Mar 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.