Patent · US Active

Gate structure for field effect transistor

US8518783B2 · kind B2 · utility

2Cited by

3References

9Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Markus Mueller · Heilbronn, DE
Guillaume Boccardi · Woluwe-Saint-Lambert - Sint-Lambrechts-Woluwe, BE
Jasmine Petry · Brussels, BE

Key dates

Filing date	Apr 27, 2009
Grant date	Aug 27, 2013
Priority date	—
Expiry date	Dec 5, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/667
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises AlxSiyOz, which has a higher relative dielectric constant value than SiO2. A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO2-based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2-based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO2-based layer to form an AlxSiyOz interfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.