High-speed processor core comprising direct processor-to-memory connectivity
US8519739B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | May 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed processor core having a plurality of individual FPGA-based processing elements configured in a synchronous or asynchronous pipeline architecture with direct processor-to-memory interconnectivity that avoids the latency and bus contention delays of FPGAs using conventional bused memory.The high-speed processor core has one or more memory structures such as SDRAM or QDR electronic memory and is electrically coupled directly to one or more FPGAs using an access lead network to provide a pipelined set of FPGA-based processor elements for processing one or more predetermined operations such as one or more detection algorithms at line rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.