PLL dual edge lock detector
US8519756B2 · kind B2 · utility
3Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.