Digital DLL including skewed gate type duty correction circuit and duty correction method thereof
US8519758B2 · kind B2 · utility
4Cited by
10References
8Claims
0Family size
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Key dates
| Filing date | Mar 11, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.