Closed-loop slew-rate control for phase interpolator optimization
US8519761B1 · kind B1 · utility
10Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | May 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.