Shift register, scanning signal line drive circuit provided with same, and display device
US8519764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2010 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Jul 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.