Low interconnect resistance integrated switches
US8519916B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/82
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.