Protection circuit for digital integrated chip
US8520350B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 26, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A protection circuit includes first and second electronic switches. When a CPU socket does not contain a CPU, a signal pin of the CPU socket outputs a high level signal. The first and second electronic switches are turned on. A data transmitting line of a SMBus is connected to a digital integrated chip. The parameters of the digital integrated chip can thus be regulated. When the CPU socket contains the CPU, the signal pin of the CPU socket outputs a low level signal. The first and second electronic switches are turned off. The data transmitting line of the SMBus is disconnected from the digital integrated chip, to prevent damage to the digital integrated chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.