Semiconductor modules and signal line layout methods thereof
US8520422B2 · kind B2 · utility
1Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | May 6, 2010 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Sep 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module and a layout method of the memory module. The memory module includes memory devices connected to corresponding tabs through corresponding damping resistors formed on a printed circuit board and includes a first signal line group in a first region between the memory devices and the damping resistors and a second signal line group in a second region between the corresponding damping resistors and the connecting terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.