Method and apparatus for testing 3D integrated circuits

US8522096B2 · kind B2 · utility

Assignee

• SYNTEST TECHNOLOGIES, INC. · US

Inventors

• Laung-Terng Wang · Sunnyvale, US
• Nur A. Touba · Austin, US
• Michael Hsiao · Blacksburg, US
• Zhigang Jiang · San Jose, US
• Shianling Wu · Princeton Junction, US

Key dates

• Filing date: Aug 31, 2011
• Grant date: Aug 27, 2013
• Expiry date: Feb 27, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318572
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.