Logic built-in self-test programmable pattern bit mask
US8522097B2 · kind B2 · utility
8Cited by
11References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2010 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Sep 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.