Correcting memory device and memory channel failures in the presence of known memory device failures
US8522122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.