Re-modeling a memory array for accurate timing analysis
US8522178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Oct 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.