Patent · US Active

Generation of an end point report for a timing simulation of an integrated circuit

US8522182B2 · kind B2 · utility

3Cited by

0References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ulrich Krauch · Waldenbuch, DE
Kurt Lind · Lörrach, DE
Alexander Woerner · Eppelheim, DE

Key dates

Filing date	Dec 8, 2011
Grant date	Aug 27, 2013
Priority date	—
Expiry date	Dec 8, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.