Method of fabricating semiconductor device with vertical channel transistor
US8524560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
Abstract
A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.