Using offset cancellation circuit to mitigate beat-frequency oscillation of phase currents in a multiphase interleaved voltage regulator
US8525497B2 · kind B2 · utility
3Cited by
6References
9Claims
0Family size
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Key dates
| Filing date | Feb 1, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1586
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
For a multiphase interleaved voltage regulator, an offset cancellation circuit is applied for each phase separately. The current loop gain of each phase is thus increased to mitigate the beat-frequency oscillation in phase currents when the beat frequency is below the bandwidth of the low-pass filter in the offset cancellation circuit, without introducing additional instability issue that is the drawback of increasing current-sensing gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.