Patent · US Active

Time-interleaved sample-and-hold

US8525556B2 · kind B2 · utility

4Cited by

4References

37Claims

0Family size

Assignee

CREST SEMICONDUCTORS, INC. · US

Inventors

Ramesh Kumar Singh · Newark, US
Yusuf A. Haque · San Jose, US
Donald E. Lewis · Mission Viejo, US

Key dates

Filing date	Jan 28, 2011
Grant date	Sep 3, 2013
Priority date	—
Expiry date	Feb 18, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/1042
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.