Phase lock loop having high frequency CMOS programmable divider with large divide ratio
US8525561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/54
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.