Patent · US Active

Circuit, an adjusting method, and use of a control loop

US8525583B2 · kind B2 · utility

0Cited by
30References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 30, 2012
Grant dateSep 3, 2013
Priority date
Expiry dateJul 30, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C5/147
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.