Non-volatile memory device
US8526225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2008 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less. The current flow when switching between resistance states is less than 10 μA. The memory cells of the device can be toggled between the resistance states, and the resistance states are non-volatile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.