Low cost and high speed architecture of montgomery multiplier
US8527570B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2010 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/728
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to perform Montgomery multiplication includes a first multiplier array configured to multiply w bits of an operand X by W bits of an operand Y, where w and W are integers and w is less than W. A second multiplier array is configured to multiply w bits of an operand Q by W bits of a modulo M. An adder array is configured to add outputs of the first and second multiplier arrays to generate a sum. A partial sum array is configured to store a left portion of the sum. A memory is configured to store a right portion of the sum. Q computation logic includes a lookup table and a half-multiplier that compute W bits of the operand Q sequentially incycles orcycles. The W bits of the operand Q are stored in the fourth buffer for use by subsequent W×W operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.