Semiconductor memory device
US8530879B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2011 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
Abstract
A semiconductor memory device in accordance with an embodiment comprises first lines, second lines, and a memory cell array including memory cells. Each of the memory cells is disposed at each of intersections of the first lines and the second lines and is configured by a rectifier element and a variable resistor connected in series. The rectifier element comprises a first semiconductor region of a first conductivity type including an impurity of a first impurity concentration, and a second semiconductor region of a second conductivity type including an impurity of a second impurity concentration lower than the first impurity concentration. The first semiconductor region and the second semiconductor region are formed by silicon. A junction interface of the first semiconductor region and the second semiconductor region is a pseudo-heterojunction formed by two layers that have different band gap widths and are formed of the same material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.