Semiconductor device and method of manufacturing the same

US8530931B2 · kind B2 · utility

Assignee

• FUJITSU SEMICONDUCTOR LIMITED · JP

Inventors

• Masayoshi Asano · Kawasaki, JP
• Junichi Mitani · Kawasaki, JP

Key dates

• Filing date: Nov 21, 2011
• Grant date: Sep 10, 2013
• Expiry date: Feb 24, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1≧A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.