Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof
US8530961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Oct 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.