Phase locked loop with digital compensation for analog integration
US8531219B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Apr 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.