Multipliers with a reduced number of memory blocks
US8533245B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.