Arrangement for generating poly-phase sequences
US8533247B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2013/0037
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The electronic circuit arrangement is used for generating poly-phase sequences as synchronization sequences and/or reference sequences in radio communications systems. It comprises a first adder, a first multiplier, a first register, a second register, a first counter and a trigonometry device. The first adder adds a value (km) formed from the value (k) of the counter to the value (B) of the first register. The first multiplier multiplies the value (A) of the second register by a value (y) formed from the value (B) of the first register and the value (k) of the counter. The trigonometry device forms the real part and the imaginary part of the present value of the poly-phase sequence (ak) from a value formed at least from the output value (wk) of the first multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.