Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses
US8533394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.