Double data rate output circuit
US8533522B2 · kind B2 · utility
1Cited by
30References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Sep 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.