Error correction circuit and method thereof
US8533573B2 · kind B2 · utility
0Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2008 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | May 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03598
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.