Integrated circuit including a hetero-interface and self adjusted diffusion method for manufacturing the same
US8536620B2 · kind B2 · utility
3Cited by
0References
9Claims
0Family size
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Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.