Hybrid process for forming metal gates of MOS devices

US8536660B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Peng-Fu Hsu · Baoshan, TW
• Yong-Tian Hou · Singapore, SG
• Ssu-Yi Li · Hsinchu, TW
• Kuo-Tai Huang · Hsinchu, TW
• Mong-Song Liang · Baoshan, TW

Key dates

• Filing date: Mar 12, 2008
• Grant date: Sep 17, 2013
• Expiry date: Jul 4, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/8314

Abstract

A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.