Tiered integrated circuit assembly and a method for manufacturing the same
US8536693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Oct 16, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.