Integrator distortion correction circuit
US8536923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45512
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing gain error and distortion in an operational amplifier due to errors in the second or integrator stage. A correction circuit may replicate an error current and insert the current into the signal stream to preempt the induction of an error at the amplifier's input. A capacitor may sample the error voltage at the input of the integrator stage of the amplifier and generate a replica of the error current in the integration capacitor to feed it into the input of the integrator stage. This eliminates any nonlinearity errors created by error currents in the compensation or integration capacitor at the second or integrator stage of the two-stage amplifier. Feeding the error current to the integrator stage may be facilitated with a unity gain buffer and a current mirror.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.