Voltage level translator circuit

US8536925B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Dipankar Bhattacharya · Macungie, US
• Makeshwar Kothandaraman · Whitehall, US
• John C. Kriz · Palmerton, US
• Bernard L. Morris · Allentown, US
• Jeffrey J. Nagy · Allentown, US
• Peter James Nicholas · Sydney, AU

Key dates

• Filing date: Dec 29, 2008
• Grant date: Sep 17, 2013
• Expiry date: Jul 6, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0375
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).