Liquid crystal display comprising first and second control thin film transistors and wherein first and second thin film transistors of adjacent rows within a same column are connected to a same column of data lines
US8537299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jun 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0213
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate comprises a plurality of pixel units defined by interacting of a plurality of gate lines along a row direction and a plurality of data lines along a column direction, and a pixel electrode formed within each of the pixel units. Each row of the pixel units are provide with a first gate line and a second gate line in the gate lines, and each of the pixel units is provides with a first thin film transistor and a second thin film transistor; the first thin film transistor is connected with the first gate line, and the second thin film transistor is connected with the second gate line; the first thin film transistor is connected with the data line at one side of the pixel unit, and the second thin film transistor is connected with the data line at the other side of the pixel unit, and the second thin film transistors of the pixel units in one row and the first thin film transistors of the pixel units in an adjacent row within the same columns are connected to the same column of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.