Test mode control circuit in semiconductor memory device and test mode entering method thereof
US8537628B2 · kind B2 · utility
5Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.