Scalable interface for connecting multiple computer systems which performs parallel MPI header matching
US8537828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface device for a compute node in a computer cluster which performs Message Passing Interface (MPI) header matching using parallel matching units. The interface device comprises a memory that stores posted receive queues and unexpected queues. The posted receive queues store receive requests from a process executing on the compute node. The unexpected queues store headers of send requests (e.g., from other compute nodes) that do not have a matching receive request in the posted receive queues. The interface device also comprises a plurality of hardware pipelined matcher units. The matcher units perform header matching to determine if a header in the send request matches any headers in any of the plurality of posted receive queues. Matcher units perform the header matching in parallel. In other words, the plural matching units are configured to search the memory concurrently to perform header matching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.