System and method of maintaining correction of DC offsets in frequency down-converted data signals
US8537942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2012 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Apr 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuitry and method for reduce test time for wireless signal systems by using dynamic adaptive correction of DC offsets generated by the test instrument. The data signal is sampled for downstream processing including during pre-, inter-, or post-packet time intervals where no packet-data signal is occurring and where the device's power amplifier is turned off. The sampled data signal is measured for a DC offset occurring during these inter-packet time gaps. Compensating DC offset values are stored in a table indexed by frequency, gain and temperature range. When a subsequent test is carried out at that frequency, gain, and temperature range, the stored compensation value is used to correct the signal. DC offsets continue to be measured, stored and applied to captured signals, continuously refining the compensation values and decreasing the need for time-intensive calibrations. When a measured DC offset exceeds pre-determined limits, the instrument undergo a calibration step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.