System and method for compensating for loop filter delay
US8537955B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Nov 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit includes a phase detector, a loop filter, a phase rotator, a predictor and a delay line. The phase detector receives an input data signal and generates a phase error signal for estimating phase error in the input data signal when referred to a recovered clock. The loop filter receives the phase error signal and determines a phase control signal based on the phase error signal. The phase rotator receives the phase control signal, and provides a phase adjusted clock based on a reference clock and the phase control signal. The predictor receives the phase error signal, and determines a delay control signal based on the phase error signal. The delay line outputs the recovered clock by delaying the phase adjusted clock from the phase rotator using the delay control signal from the predictor, and provides the recovered clock to the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.