Techniques for generating fractional periodic signals

US8537956B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Tien Duc Pham · San Jose, US
• Leon Zheng · San Jose, US
• Sergey Shumarayev · Los Altos Hills, US
• Zhi Y. Wong · San Jose, US
• Paul Ekas · Seattle, US

Key dates

• Filing date: Nov 24, 2010
• Grant date: Sep 17, 2013
• Expiry date: Nov 11, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04J3/062
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.