Flexible architecture and instruction for advanced encryption standard (AES)
US8538015B2 · kind B2 · utility
40Cited by
13References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Apr 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flexible instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.