Buffer circuit with integrated loss canceling
US8538367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2009 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A filter circuit enhances a deficient Q-value in a filter stage and buffers the filter stage from subsequent filter stages using a common active device. A filter circuit includes a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal and a first Q-enhancement buffer stage. The first Q-enhancement buffer stage is coupled to the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. A filtering method includes filtering an input signal in a first Q-deficient filter stage and enhancing a deficient Q-value of the first Q-deficient filter stage with an active device. The method further includes buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.