Bus arbitration techniques to reduce access latency
US8539129B2 · kind B2 · utility
17Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of arbitrating requests from bus masters for access to shared memory in order to reduce access latency, comprises looking ahead into currently scheduled requests to the shared memory and predicting latency of the requests based on characteristics of the currently scheduled requests, such as increasing page hit rate, or balancing read and write traffic. The requests are scheduled based at least in part on the predicted latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.