Cache coherency within multiprocessor computer system
US8539164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2008 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.